Technical Field
The present disclosure generally relates to the field of semiconductor devices. More particularly, the present disclosure relates to vertical gate MOS field effect transistors (or VTMOS, “Vertical Trench-MOS”).
Description of the Related Art
A VTMOS transistor integrated on a chip of the semiconductor material comprises a drain region at a rear surface of the chip, a source region at a front surface of the chip opposite the rear surface, and a gate region in a trench extending in the chip from the front surface. More particularly, the walls of the trench are coated with a layer of insulating material (typically, gate oxide), and the trench is filled with a conductive material (typically, polycrystalline silicon or polysilicon).
During operation, a channel region is created along the walls of the trench, between the source region and the drain region. In this way, in the case of a small size of the VTMOS transistor (for example, for making electronic circuits having high integration density), the channel region may be maintained sufficiently long to prevent short channel effects (for example, punch-through or permanently shorted channel) and unwanted changes in characteristic electrical parameters (for example, transconductance).
Although widely used, the VTMOS transistors have drawbacks that preclude a wider deployment thereof, for example, in power applications.
In such applications, the VTMOS transistors, being affected by relatively high voltages and/or currents (for example, 1-500 A and 10-100V), are subject to considerable heating; an excessive and/or prolonged heating (or overheating) may cause damages or breakages of the VTMOS transistor even after relatively short periods of use.
In order to avoid that, different solutions are based on the common approach of monitoring the current through the VTMOS transistor, and turn it off when it exceeds a predefined value (associated with an overheating condition). However, such approach involves operation errors, such as false detections of overheating conditions. This is due to the fact that the current monitoring does not allow distinguishing between short-circuit current—which, lasting for typically long times, determines the overheating of the transistor—and switching current—which, limited to a short time interval corresponding to a switching, does not instead determine an appreciable overheating. Furthermore, in the case where the short-circuit current is lower than the predefined value, but lasting for a time sufficiently long to overheat the transistor, the overheating condition is not detected.
A different approach provides for detecting the temperature of the transistor. In a typical implementation, two conductive regions having opposite doping are integrated onto the chip together with the VTMOS transistor to form a corresponding thermal diode; in this way, by exploiting the (inverse) proportionality between the voltage drop across a forward-biased diode and its junction temperature, it is possible to detect the overheating condition in an appropriate manner.
However, the solutions based on such approach are not satisfactory in terms of electrical performance. In fact, as the thermal diode is typically buried within the chip, it affects the current through the VTMOS transistor. In addition, unavoidable couplings between the conductive regions of the diode and the conductive regions of the VTMOS transistor adjacent thereto may determine parasitism (for example, parasitic diodes and/or BJT transistors) able to modify the functioning of the VTMOS transistor and of the thermal diode.
In addition, the presence of the trench reduces the available space on the chip where to make the thermal diode; this makes the establishment of couplings between the conductive regions of the thermal diode and the conductive regions of the VTMOS transistor even more likely (which requires more effort design).